1. Field of the Invention
The invention relates to an insulated-gate semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
Power devices manufactured by using SOI (silicon on insulator) substrates are known. Thick film SOI substrates are used for vehicular engine control and in drive circuits of plasma displays because they make it possible to isolate devices from each other easily by forming trenches and possible to suppress variations in manufacturing because they have a thick silicon layer. Example power devices that are manufactured by using SOI substrates include IGBTs (insulated-gate bipolar transistors) and MOSFETs (metal oxide semiconductor field-effect transistors).
Examples of power devices having conventional structures will be described below. In this disclosure and the accompanying drawings, symbols n and p that refer to layers or regions indicate that carriers of the layers or regions are electrons and holes, respectively. Superscripts “+” and “−” that accompany symbols n or p to form symbols n+ and n−, for example, indicate that the impurity concentrations of semiconductors that are given the symbols n+ and n−, for example, are higher than and lower, respectively, than the impurity concentration of a semiconductor that is given the symbol n, for example.
FIGS. 22-27 show the configurations of example power devices having conventional structures. In a semiconductor device 100 shown in FIG. 22, a buried oxide (BOX) region 102 is formed on the surface of a support substrate 101. A high-resistivity n− drift region 103 is formed on the surface of the BOX region 102. Therefore, the BOX region 102 insulates the n drift region 103 and the support substrate 101 from each other. A p-type body region 104 is formed as a partial surface region of the n drift region 103. An n+ emitter region 105 which is lower in resistivity than the n− drift region 103 is formed as a partial surface region of the p-type body region 104 and a p+ contact region 106 is formed as another partial surface region of the p-type body region 104 so as to be in contact with the n+ emitter region 105. Part of the p+ contact region 106 is located under part of the n+ emitter region 105.
An n-type buffer region 107 which is lower in resistivity than the n− drift region 103 is formed as a partial surface region of the n− drift region 103 so as to be disposed away from the p-type body region 104. A p+ collector region 108 which is lower in resistivity than the p-type body region 104 is formed as a partial surface region of the n-type buffer region 107.
An insulating film 109 is laid on part of the surface of the p+ collector region 108, the surface of the n-type buffer region 107, and part of the surface of the n− drift region 103. A gate insulating film 110 is laid on part of the surface of the n+ emitter region 105, the surface of the p-type body region 104, and part of the surface of the n− drift region 103 so as to be in contact with the insulating film 109. A gate electrode 111 is formed over the n+ emitter region 105, the p-type body region 104, and the n− drift region 103, with the gate insulating film 110 and part of the insulating film 109 interposed between the gate electrode 111 and the p-type body region 401.
An emitter electrode 113 is formed so as to be in contact with the n+ emitter region 105 and the p+ contact region 106 and thereby short-circuits them. A collector electrode 114 is formed so as to be in contact with the p+ collector region 108. The semiconductor device 100 shown in FIG. 22 thus is a lateral IGBT structure. If the p+ collector region 108 is replaced by an n-type region that is lower in resistivity than the n-type buffer region 107, the resulting semiconductor device is a MOSFET structure.
In the semiconductor device 100, a pnp bipolar transistor includes the p+ collector region 108, the n-type region consisting of the n-type buffer region 107 and the n− drift region 103, and the p-type body region 104. An npn bipolar transistor includes the n+ emitter region 105, the p-type body region 104, and the n drift region 103 which constitutes a parasitic thyristor. To prevent latch-up that would otherwise be caused by the parasitic thyristor, an upper limit is set for the on-current.
The upper limit of the on-current can be increased by preventing the npn bipolar transistor from operating. This is attained by decreasing the resistance of a current path 115 that extends from the end of the channel to the p+ contact region 106 past the portion located under the n+ emitter region 105. In the following, this current path will be referred to as “under-emitter current path.”
Next, a method for reducing the resistance of the under-emitter current path 115 will be described. A semiconductor device 200 shown in FIG. 23 is described in JP-A-2005-109226, US 2002/125542A1 (corresponds to JP-A-2002-270844), and D. R. Disney et al., “SOI LIGBT Devices with a Dual p-Well Implant for Improved Latching Characteristics,” Int. Sym. Power Semi. Dev. ICs 1993, pp. 254-258. In the semiconductor device 200 shown in FIG. 23, a p+ low-resistivity region 141 which is lower in resistivity than the p-type body region 104 is formed under the n+ emitter region 105 and the p+ contact region 106, whereby the resistance of the under-emitter current path 115 is reduced. The low-resistivity region 141 is formed by ion implantation. Layers, regions, etc. having similar features as those in FIG. 22 are given the same reference symbols as the latter and will not be further described.
Uncertainty in the length of the under-emitter current path 115 is eliminated and that length is minimized by forming the low-resistivity region 141 under the n+ emitter region 105 using the gate electrode 111 as a mask. The method for forming the low-resistivity region 141 that can be self-aligned with the gate electrode 111 in the above manner is known (refer to U.S. Pat. No. 5,079,602 (corresponds to JP-B-8-17233) and Philip K. T. Mok et al., “A Self-aligned Trenched Cathode Lateral Insulated Gate Bipolar Transistor with High Latch-up Resistance,” IEEE Transactions on Electron Devices, Vol. 42, No. 12, December 1995, pp. 2,236-2,239, for example).
Another method is known in which to lower the current amplification efficiency of the npn transistor a p-type low-resistivity region which is lower in resistivity than the p-type body region is formed as a bottom region of the p-type body region.
Next, a description will be made of semiconductor devices in which a low-resistivity region is formed as a bottom region of the p-type body region.
A semiconductor device 300 shown in FIG. 24 is described in the above-mentioned U.S. Pat. No. 5,079,602. In the semiconductor device 300 shown in FIG. 24, an n− drift region 103 is formed on the surface of a low-resistivity p+ substrate 301. A p-type body region 104 is formed as a partial surface region of the n− drift region 103. An n+ emitter region 105 is formed as a partial surface region of the p-type body region 104. A trench 302 is formed approximately at the center of the p-type body region 104 so as to be adjacent to the n+ emitter region 105. An emitter electrode 113 is formed on the inside surface of the trench 302 so as to electrically connect the p-type body region 104 and the n+ emitter region 105. A gate electrode 111 is formed on part of the surface of the n+ emitter region 105, the surface of the p-type body region 104, and part of the surface of the n drift region 103 with a gate insulating film 110 interposed in between. A p+ low-resistivity region 142 which is lower in resistivity than the p-type body region 104 is formed in the p-type body region 104 around the bottom surface of the trench 302. The p+ low-resistivity region 142 is formed by diffusing a high-concentration p-type impurity from the bottom surface of the trench 302. A collector electrode 114 is formed on the surface of the p+ substrate 301 which is opposite to its surface that is in contact with the n− drift region 103.
A semiconductor device 400 shown in FIG. 25 is described in JP-A-6-24430. In the semiconductor device 400 shown in FIG. 25, an n− drift region 103 is formed on the surface of a p+ substrate 301. A p-type body region 104 is formed as a partial surface region of the n drift region 103. An n+ emitter region 105, an n+ first region 401, and an n+ second region 402 are formed as partial surface regions of the p-type body region 104 so as to be spaced from each other. A first gate electrode 111a is formed on the surface of that portion of the p-type body region 104 which is located between the n− drift region 103 and the n+ emitter region 105 with a first gate insulating film 110a interposed in between. A second gate electrode 111b is formed on the surface of that portion of the p-type body region 104 which is located between the n+ first region 401 and the n+ second region 402 with a second gate insulating film 110b interposed in between. A first emitter electrode 113a is formed so as to be in contact with the n+ emitter region 105, and a second emitter electrode 113b is formed so as to be in contact with the n+ second region 402. The first emitter electrode 113a and the second emitter electrode 113b are connected to each other electrically. A short-circuiting electrode 403 short-circuits the p-type body region 104 and the n+ first region 401.
A p+ low-resistivity region 142 which is lower in resistivity than the p-type body region 104 is formed under the n+ emitter region 105, the n+ first region 401, and the region located between these regions around the boundary between the p-type body region 104 and the n− drift region 103. A p+ diffusion region 143 is formed, by boron ion implantation and thermal diffusion, as a partial surface region of the p-type body region 104 between the n+ emitter region 105 and the n+ first region 401 so as to be in contact with the p+ low-resistivity region 142. The p+ diffusion region 143 partially occupies the region under the n+ emitter region 105 and the region under the n+ first region 401 and has approximately the same width as the p+ low-resistivity region 142. A collector electrode 114 is formed on that surface of the p+ substrate 301 which is opposite to its surface that is in contact with the n− drift region 103.
A semiconductor device 500 shown in FIG. 26 is described in U.S. Pat. No. 7,268,045. In the semiconductor device 500 shown in FIG. 26, an n− well layer as an n− drift region 503 is formed on the surface of a p+ or p− epitaxial substrate 501. A p-type body region 504 is formed as a partial body region of the n− drift region 503. An n++ source region 505 and a p++ contact region 506 which is in contact with the n++ source region 505 are formed as partial surface regions of the p-type body region 504.
An n-type buffer region 507 which is lower in resistivity than the n− drift region 503 is formed as a partial surface region of the drift region 503 so as to be spaced from the p-type body region 504. An n++ drain region 508 is formed as a partial surface region of the n-type buffer region 507. A source electrode 513 is formed so as to be in contact with the n++ source region 505 and the p++ contact region 506 and short-circuits them. An insulating film 509 is laid on part of the surface of the n++ drain region 508, the surface of the n-type buffer region 507, and part of the surface of the n− drift region 503. A gate electrode 511 is formed on part of the surface of the n++ source region 505, the surface of the p-type body region 504, and part of the surface of the n− drift region 503 with a gate oxide film 510 and part of the insulating film 509 interposed in between. A drain electrode 514 is formed so as to be in contact with the n++ drain region 508. A p+ low-resistivity region 145 which is lower in resistivity than the p-type body region 504 is formed under the n++ source region 505 and the p++ contact region 506 around the boundary between the n− drift region 503 and the p-type body region 504. The p+ low-resistivity region 145 is formed by ion implantation with a high acceleration energy and epitaxial growth.
A semiconductor device 600 shown in FIG. 27 is described in the above-mentioned D. R. Disney et al., “SOI LIGBT Devices with a Dual p-Well Implant for Improved Latching Characteristics,” Int. Sym. Power Semi. Dev. ICs 1993, pp. 254-258. The semiconductor device 600 shown in FIG. 27 is manufactured by using an SOI substrate. The SOI substrate is configured in such a manner that an n− drift region 103 is laid on a support substrate (not shown) with a BOX region 102 interposed in between. A p-type body region 104 is formed as a partial region of the n drift region 103 so as to be in contact with the BOX region 102. A p+ low-resistivity region 146 which is lower in resistivity than the p-type body region 104 is formed as a partial region of the p-type body region 104 so as to be in contact with the BOX region 102. An n+ emitter region 105 is formed as a partial surface region of the p+ low-resistivity region 146.
The p+ low-resistivity region 146 is formed after formation of a gate electrode 111 by ion implantation using the gate electrode 111 as a mask and thermal diffusion. Therefore, the p+ low-resistivity region 146 is self-aligned with the gate electrode 111. A diffusion lateral expansion region 147 is formed in such a manner that the p+ low-resistivity region 146 expands to under a gate insulating film 110 due to the lateral range of ions of the ion implantation and lateral thermal diffusion of ions.
The ion implantation may be performed either perpendicularly or slantingly with respect to the substrate. For example, U.S. Pat. No. 6,528,848B1 (corresponds to JP-A-2001-94094) discloses a radio-frequency laterally double-diffused MOSFET (RF LDMOST) which is manufactured by using a bulk substrate. In the following, the laterally double-diffused MOSFET will be referred to as LDMOST. US 2006/118902A1 (corresponds to JP-A-2006-165145) discloses an LDMOST which is manufactured by using an SOI substrate.
However, in the above techniques, the acceleration energy of the ion implantation needs to be set high because the low-resistivity region where the under-emitter current path is formed is formed by performing ion implantation in a self-aligned manner using the gate electrode as a mask. This raises a problem that the gate electrode should be so thick that ions do not pass through it at the time of the ion implantation. For example, where boron atoms are implanted at an acceleration energy of 90 keV, the thickness of the gate electrode should be 0.6 μm or more. However, in power ICs, with the recent requirement of miniaturization, the thickness of the gate electrode is generally 0.4 μm or less. Therefore, there is a problem that the above-described conventional techniques are not suitable for integration with logic circuits.
In the semiconductor device shown in FIG. 23, the current amplification efficiency of a first npn bipolar transistor which is composed of the n+ emitter region 105, the p+ low-resistivity region 141, the p-type body region 104, and the n− drift region 103 is lowered by the p+ low-resistivity region 141. However, there is a problem that since a second npn bipolar transistor which is composed of the n+ emitter region 105, the p-type body region 104, and the n− drift region 103 does not include the p+ low-resistivity region 141, its current amplification efficiency is not lowered and hence is prone to a latch-up phenomenon.
A method for lowering the manufacturing cost by reducing the device area by shortening the channel length and thereby increasing the current density is known. However, in this case, the base of the second npn bipolar transistor is made thinner (i.e., the Gummel number of the base becomes smaller) and the current amplification efficiency of the transistor is increased. This results in a problem that the entire device becomes prone to the latch-up phenomenon. The Gummel number satisfies a relationship(Gummel number)∞∫p(r)drwhere p(r) is the hole density at the position r.
The latch-up phenomenon can be made less likely to occur by forming the low-resistivity region in a portion of the p-type body region that is close to the n+ emitter region than in a bottom portion of the p-type body region. The reason is as follows. While the bipolar transistor is on, electrons flow through the channel region that is formed around the boundary between the gate insulating film and the p-type body region and holes flow from the p+ collector region to the n− drift region. Since a strong Coulomb force acts between electrons and holes, after holes enter the p-type body region, most of the holes flow immediately under the channel toward the p+ contact region.
In each of the vertical devices shown in FIGS. 24 and 25, the latch-up phenomenon cannot be suppressed because the low-resistivity region is formed in the bottom portion of the p-type body region. And there is another problem that the impurity concentration of the p+ low-resistivity region is limited so as not to lower the breakdown voltage of the pn junction formed by the n− drift region and the p-type body region.
The above-mentioned US 2006/118902A1 states that in the p+ low-resistivity region the range of the ion implantation, that is, the maximum impurity concentration position of the ion implantation, is approximately the same as the maximum position of an impurity concentration profile of the lateral extension of the diffusion. This means a problem that the width of the p+ low-resistivity region cannot be made greater than that of the lateral extension of the diffusion.
It is known that an insulated-gate transistor such as an IGBT or a MOSFET is destructed mainly in the following two cases. The first case is that the collector (drain)-emitter voltage becomes too high in an on state. This condition may be called FUL fault under load). The second case is that the IGBT is turned off in a state that the collector-emitter voltage is fixed at a large value, that is, the resistance to short-circuiting is exceeded (HSF: hard switching fault). To increase the resistance to short-circuiting, a device structure is necessary which can suppress the latch-up phenomenon more effectively than the above-described conventional structures.